THE DAQ COMPONENTS

Magic Box Frontend

The Magic Box is a rack mountable, FPGA based, real-time timing control module for the µLan experiment. The MB is controlled and monitored from a standard PC via an IEEE1284 Enhanced Parallel Port connection.The front panel, shown below, contains a number of interface elements:

1. A single green LED, +5V power supply indicator in the upper left corner.
2. A single red LED, -5V power supply indicator in the upper left corner.
3. A single SMA panel jack for the input timebase; it takes an LVTTL (+3.3 V) square wave clock signal up to approximately 45 MHz.
4. Two, 34 pin ribbon cable connectors. In each connector, the left-most pair is digital ground; each remaining pair is a NECL differential output. The outputs are numbered from left to right, outputs 0 through 31.
5. Four yellow LEDs for displaying various status information.

The time structure of the experiment is divided into a four tiered hierarchy: runs contain segments, segments contain fills and fills contain one accumulation period and one measurement period.

There are four types of output pulses that the magic box generates: fill marker pulses, fill active pulses, segment marker pulses and segment active pulses.

There are a large number of registers in the register set. There are both stateless and stateful registers.

The stateful registers are divided into three groups:
1. Pulse register groups: Within each group are the registers controlling the parameters of each ECL output channel. The absolute address for each register group is the same as the ECL channel number. Different types of output pulsers require different numbers of registers for specifying their operating parameters, but the registers have been named generically, and are located at the same offset addresses for each type.

In addition, all pulser outputs have a three bit status register containing the following information:
1. Bit 0: Enable bit. The pulse channel is enabled if this bit is set to one (1), and disabled if set to zero (0).
2. Bit 1: Polarity bit. Allows one to switch between negative and positive logic levels. A value of zero selects positive logic, that is, the output pulses high and sits low; a value of one (1) on the other hand selects negative logic, with the output pulsing low and sitting high.
Bit 2: Fill skip bit.

2. Top Level register group: This group contains control parameters associated with the global operation of the MB. These live in their own address space unique from all of the Pulse register groups. The registers in the Top Level Register Group control the following behaviors:

3. Stateless Registers:
    Register Name    Absolute Address
Global Reset               135
Pause                       23
Unpause                     31
AAR                         15

Regardless of the state of previous writes, address writes to the given absolute addresses access the above listed stateless registers. The first three registers contain no data; merely accessing the address performs the given function. The AAR is a stateless register that maintains the state for the stateful register groups.

The MIDAS frontend for the magic box shown below contains a bunch of ODB entries in a subdirectory /Equipment/MB/Settings that contain operating parameters.

Basic instructions for writing to the Magic Box are:
1. Before writing to any register one must pause the device. This can be achieved either by globally resetting (address 135) or by invoking the 'pause' address (address 23). To unpause, invoke address 31.
2. Once the device is paused, write the offset address of the pulse or signal in mind to the absolute address. The absolute address is address 15. Top level elements in the magic box correspond to offset address 64. Top level elements include such applications as the fill length, segment length, heartbeat and the segment sounter. Non-top level elements (pulse elements) are identified by their corresponding channels (0-17) and this channel number should be written to the absolute address when manipulating the pulses associated with the channel. Different pulses have varying numbers of addresses to write to depending on the type of pulse. Fill marker pulses have one time signal and one status signal. Fill active pulses and segment marker pulses have two time signals and one status signal. Segment active pulses have four time signals and one status signal. Each time signal is broken down into two addresses, the first corresponding to the first byte (bits 0-7) and the second corresponding to the second byte. The status address (always address 4) can take on values of 0 or 1.
3. Here we show an example of how we would write some data to channel 13:
> a 135 --global reset
> a 15 --invokes absolute address
> d 13 --writes channel address to absolute address
> a 0 d 10 --writes 10 to first time signal address first byte
> a 128 d 0 --writes 0 to first time signal address second byte
> a 1 d 15 --writes 15 to second time signal address first byte
> a 129 d 0 -- writes 0 to second time signal address second byte
> a 2 d 20 a 130 d 0 a 3 d 25 a 131 d 0 --writes data to other time signals
> a 4 d 1 --writes 1 to status bit (makes it active)
> a 31 --unpause
> a 23 -- pause
The Magic Box frontend is run either from the programs page on the MIDAS web interface or from the frontend processor by typing ./femagic -h be01 -e mulan from the sub-directory /home/mulan/magic_box.